This disclosure relates generally to semiconductor processing and more specifically to scanner equipment used in photolithography. Lithography is widely used in integrated circuit (IC) fabrication. A material layer is deposited on a wafer. A masking material is formed over the material layer and exposed in a pattern to form a hard mask for etching. Portions of the material layer which are not covered by the mask are then etched to form one or more patterns (e.g., trenches) that are filled with conductive material (e.g., copper) and planarized to form circuit paths. Another material layer is deposited over the patterned first material layer and the process is repeated to pattern the second layer. This process is repeated many times.
To ensure proper connectivity and performance, the patterns in adjacent layers are aligned properly with each other. Alignment marks (e.g., boxes) are used to align each added layer to the previously formed layer.
To maintain proper alignment between layers, a form of run-to-run control referred to as advance process control (APC) is used. Alignment errors are monitored. From time to time, an operator inputs a correction (e.g., a translation, rotation or scaling correction) to the scanning exposure tool, perhaps weekly or monthly. This correction is applied to compensate for the condition causing the misalignment.